Generally, sense amplifier circuitry for sensing data stored in a CMOS DRAM cell includes a sensing clock driver, a restore clock driver, a delay section, and a sense amplifier.
Both the sensing clock signal for sensing data from the memory cell and the restore clock signal for restoring the memory cell data increase the peak current if they have steep slopes when being switched from a high level to a low level or from a low level to a high level. This increased peak current will create noise, causing the sense amplifier circuitry to produce errors.
The conventional solution for such drawbacks is to modify the steeply varying slope into a two-step or multistep slope during the switching process of the sensing clock and the restore clock, resulting in a clock signal having a gentle slope.
The conventional circuitry of the sense amplifier driver is illustrated in FIG. 1, which shows the characteristics described above.
However, in spite of the merits described above, this conventional sense amplifier circuitry has shortcomings as described below.
When the precharge operation is initiated for the sense amplifier after completing the sensing and restoring operations, the MOS transistors within the sensing clock driver are simultaneously turned on within a short period of time, due to the delaying effect of the trailing edges of the restore clock signal and the sensing clock signal. The delaying effect is caused by the multislope characteristics of the sensing clock and the restore clock signals. The simultaneous activation of these MOS transistors will dissipate the DC current through a DC current path. The MOS transistors within the restore clock driver will also form DC current paths together with those in the sense amplifier driver, whereby the DC current is dissipated. This will cause the problem of substantial dynamic power loss throughout the entire high density memory device.